1. Field of the Invention
The present invention relates generally to tuning of arbitration circuitry in a system and more specifically to circuit structures and methods within an arbiter circuit for gathering statistical information useful in tuning parameters associated with operation of the arbiter circuit.
2. Discussion of Related Art
In electronic systems it is generally known that multiple devices may share access to a common resource. For example, multiple master devices may communicate with multiple slave devices through a shared interface bus. Or for example, multiple master devices may exchange information with a shared memory device through a memory controller. In such systems it is common to utilize an arbiter circuit to arbitrate requests for temporary exclusive access by master devices for utilization of the shared resource. The arbiter generally receives requests for access to the shared resource from one or more of the multiple master devices and through any of several well-known techniques selects the next requesting master devices to receive temporary exclusive access to the shared resource. When a first master device completes its utilization of the shared resource, it relinquishes its temporary exclusive control over the shared resource by so signaling the arbiter. The arbiter then determines a next requesting master device to receive temporary exclusive control of the shared resource.
It is also generally known in the art that arbiter devices may have programmable parameters useful in tuning operation of the arbiter for specific system applications. For example, an arbiter may tune its operation to prefer master devices requesting exclusive control for purposes of write operations to a memory versus read operations, or vice versa. Or for example, an arbiter may tune its operation to preferred particular prioritized devices over lower priority master devices. Further, an arbiter may force a master device to relinquish temporary exclusive control in response to certain detected events such as expiration of a predetermined timeout, requests by other higher priority master devices, etc.
Determination of what programmable values and algorithms within and arbiter are to be selected for a particular system application can be a difficult process. Configuring an arbiter to function optimally in a particular system application requires observation over a period of time of the performance of the arbiter operating under various sequences, states and scenarios. Characteristics of the system in which the arbiter operates such as the type and quantity of data processed, execution parameters associated with the master devices requesting temporary exclusive control through the arbiter, etc. may change dramatically and dynamically through operation of the system. To properly analyze these parameters can require collection of significant amounts of representative data for subsequent analysis. Such data often cannot be determined by external observation of the results of the arbitration process. Rather, effective analysis requires acquisition of parameters and operation within the arbiter circuit per se.
Such information can often be acquired through simulation techniques stimulating operation of the arbiter in a simulated system environment. Simulation of complex circuits can be a time-consuming process because simulation of high-speed circuits is significantly slower than actual operation of the high-speed circuits. The time required for gathering representative data for analysis of optimal arbiter configuration further exacerbates the problem because the volume of data can be substantial. Meaningful statistical bases for configuration analysis require a large volume of representative data. Further, simulation techniques require the user to generate substantial volumes of input stimuli for the simulation process to generate desired sequences and scenarios for testing the arbiter. Creation of such input data sets (stimuli) to produce statistically meaningful analysis data can be difficult, especially when the properties of the data set (stimuli) may be altered by changes in the arbitration parameters.
External test and measurement equipment such as logic analyzers and oscilloscopes applied to external signals of the arbiter can detect events and count detected events over a predetermined period of time. However, such techniques generally cannot access internal information within the arbiter circuit per se. Rather, such external test and measurement equipment has visibility only to signals made available external to circuits on standard I/O pads of the circuit containing the arbiter. Addition of I/O pads for every signal related to the events of interest to the designer would add unacceptable cost and complexity to the design of the arbiter and its associated integrated circuit package.
It is evident from the above discussion that a need exists for improved methods and structures for measuring arbitration performance for purposes of tuning or reconfiguring arbitration techniques and parameters for particular system applications.
The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing methods and structures preferably integrated with the arbiter circuit for accumulating performance information during real-time execution of the arbiter circuit. In particular, the present invention in a first preferred embodiment provides a timer function integrated with the arbiter circuit for detecting a predetermined period of time over which statistical arbitration data may be accumulated. When the timer component indicates that statistical gathering is to take place, other data gathering circuits of the present invention detect particular sequences, states and signals (events) of interest to the designer and count the number of occurrences of each such event. Preferably, a plurality of such data gathering circuits are integrated with the arbiter circuit and coupled to the timer function to permit data gathering for a significant number of events of interest over an extended period of real-time arbiter operation. Off-line analysis of the gathered statistical data then permits improved configuration and selection of arbitration techniques and parameters for tuning arbitration in a particular system application.
Preferably, each data gathering circuit may be adapted flexibly to detect a variety of events of interest to the designer. Exemplary of such events to be counted are the number of clock cycles during arbitration operation during which a request is pending from any master device associated with the arbiter, the number of times read requests are followed by write requests and vice versa, the number of read requests and the number of write requests issued through the arbiter for the shared device, the number of arbiter cycles spent in a specific state of a particular state machine within the arbiter circuit, etc. Numerous other events of interest to a system designer will be readily apparent to those of ordinary skill in the art.
The architecture of the present invention provides for gathering of any and all such events and counting the number of occurrences of such events over a determined period of time.
A first feature of the invention provides a circuit for measuring statistical information regarding performance of an arbiter that arbitrates for access by multiple master devices to a shared resource, the circuit including: a programmable timer for counting a predetermined time period; and an event counter coupled to the programmable timer for counting the number of occurrences of a predetermined event within the arbiter.
Another aspect of the invention further provides a clear signal path coupled to the event counter such that a clear signal is applied to the clear signal path to reset the event counter when the programmable timer is started.
Another aspect of the invention further provides that the event counter is cleared by writing a zero value to the event counter.
Another aspect of the invention further provides that the event counter is cleared after being read by a host system.
Another aspect of the invention further provides a count enable signal path coupled to the event counter such that an enable signal is applied to the count enable signal path indicating that the predetermined time period has not yet expired in the programmable timer.
Another aspect of the invention further provides that the event counter counts events only when the enable signal is applied to the count enable signal path.
Another aspect of the invention further provides a plurality of event counters coupled to the programmable timer for counting the number of occurrences of a plurality of predetermined events within the arbiter.
Another aspect of the invention further provides that the event counter comprises: a counting circuit portion for counting a number of event signals applied as an input to the counting portion; and an event specific circuit portion coupled to the counting circuit portion for generating the event signals in response to sensing the predetermined event.
A second feature of the invention provides a method for tuning an arbiter for optimal performance in a system, the method comprising the steps of: enabling the counting of occurrences of predetermined events in the arbiter; operating the arbiter in the system; sensing occurrences of the predetermined events in the arbiter; counting sensed occurrences of the predetermined events in response to enabling of the counting; reading counts of the sensed occurrences; and reconfiguring parameters associated with operation of the arbiter based on analysis of the counts.
Another aspect of the invention further provides for clearing previously counted sensed occurrences.
Another aspect of the invention further provides that the step of clearing comprises the step of: clearing the previously counted sensed occurrences in response to the step of reading.
Another aspect of the invention further provides that the step of enabling comprises the step of writing a time period value to a timer register, and that the step of clearing comprises the step of clearing the previously counted sensed occurrences in response to the step of writing.
Another aspect of the invention further provides that the step of enabling comprises the step of writing a time period value to a timer register, and that the step of clearing comprises the step of writing a zero value to the event counter.